Implementation of Circuit Optimization Technique for Digital CMOS Comparator Using Parallel Prefix Tree Architecture

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Provided by: Iosrjournals
Topic: Hardware
Format: PDF
The digital comparator using CMOS cells that adopt the parallel prefix tree architecture. This comparator begins from most significant bit towards bit-wise least significant bit when two compared bits are equal. Using circuit optimization technique it reduced by 642 transistors from total area of 768 and also maximum fan-in and fan-out drives of five and four respectively and 1.78mW dynamic power dissipation for 16-bit (N) with 7 CMOS gate delay. The tanner EDA tool simulation for 16-bit is realized using 0.18-µm CMOS process technology with minimum supply voltage of 2.45V.
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