Implementation of CRC and Viterbi Algorithm on FPGA

Provided by: IRD India
Topic: Hardware
Format: PDF
Cyclic Redundancy Codes (CRCs) code provides a simple, yet powerful, method for the detection of errors during digital data transmission and storage. Convolutional COding and DECoding (CODEC) is a Forward Error Correction (FEC) technique that is particularly suited for a channel in which the transmitted signal is corrupted mainly by Additive White Gaussian Noise (AWGN). The Viterbi Algorithm (VA) has been widely applied for decoding convolutional encoded data in digital communication systems over the last 30 years. In this paper, the implementation of CRC and Viterbi decoder on FPGA is presented.

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