Implementation of Double Precision Floating Point Multiplier on FPGA

Provided by: International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (IJAREEIE)
Topic: Hardware
Format: PDF
Multiplication is one of the common arithmetic operations in Digital Signal Processing (DSP) computations. The proposed design is an implementation of an IEEE-754 double precision floating point multiplier, which is better when compared to a single precision multiplier because of its wider dynamic ranges and accuracy. A double precision multiplier is designed using Xilinx 12.4 ISE tool and the design verification was done on Xilinx Vertex-4 ML403 platform which handles overflow, underflow cases and truncation mode.

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