Implementation of Energy-Efficient Low Power 10T Full-Adder

In this paper, the performance of 10-tranistor based full adder is analyzed and compared with that of two different types of full adder based on Swing Restored Complementary Pass-transistor Logic (SR-CPL) XOR/XNOR logic gate and Double Pass-transistor Logic (DPL) based CMOS Full Adder is designed using Tanner EDA Tool based up on 0.25 um CMOS Technology. As part of this, the authors have performed the simulation of CMOS full adder using TSPICE and BSIM3v31 tools of Tanner EDA. The parameters of power consumption, area, propagation delay, and Power-Delay Product (PDP) are evaluated to analyze the proposed low power full adder.

Provided by: International Journal of Engineering Sciences & Research Technology (IJESRT) Topic: Hardware Date Added: Aug 2013 Format: PDF

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