Implementation of Enhanced 64-Bit Binary to Floating Point Converter Using Verilog

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Provided by: Creative Commons
Topic: Hardware
Format: PDF
Computation with floating point arithmetic is an indispensable task in many VLSI applications and accounts for almost half of the scientific operations. Also adder is the core element of complex arithmetic circuits, in which inputs should be given in standard IEEE 754 format. The main objective of the work is to design and implement a binary to IEEE 754 floating point converter for representing 64 bit double precision floating point values. The converter at the input side of the existing floating point adder/subtractor and multiplier module helps to improve the overall design.
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