Implementation of Fault Tolerant Method Using BCH Code on FPGA

Provided by: International Journal of Soft Computing and Engineering (IJSCE)
Topic: Data Management
Format: PDF
The fault tolerance degradation is the property that enables a system (often computer-based) to continue operating properly in the event of the failure of (or one or more faults within) some of its components. To designing a new 32-bit Arithmetic Logic Unit (ALU) that is secure against many attacks or faults and able to correct any 5-bit fault in any position of its 32 bits input register of ALU. Because the radiation effects on electronic circuits may cause to be inverted data bits of registers or memories.

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