Implementation of Floating Point Adder on Reconfigurable Hardware and Study Its Effect on Chip Area
Addition is the most complex operation in a floating point unit and can cause major delay while requiring a significant area. Floating point adders are hard to implement on reconfigurable hardware because floating point addition is the most complex operation since the alignment of mantissa is required before mantissa addition. Various parameters are outlined such as clock period, combinational delay, chip area i.e. number of slices, clock speed, etc. when the authors implement floating point adder on reconfigurable hardware. Implementation of floating point adder on different FPGAs causes change in consumption of chip area on using different reconfigurable hardware.