In today's life floating point adders are used in number of applications such as air traffic controller, robots, DSP processors, math processors, digital computer so the main objective is to reduce chip area and combinational delay i.e. latency it is nothing but the time required to travel an input to the output. Less is the combinational delay more faster is response and better is the implementation of adder. The implementation of floating point adder on Virtex 4 using sequential and concurrent processing family causes change in their consumption of chip area combinational delay i.e. combinational delay is less in Virtex family with the more speed grade as compared with spartan family.