Implementation of Full Adder Cells Using NP-CMOS and Multi-Output Logic Styles in 90nm Technology

In this paper, the authors present two novel 1-bit full adder cells in dynamic logic style. NP-CMOS (Zipper) and multi-output structures are used to design the adder blocks. Characteristic of dynamic logic leads to higher speeds than the other standard static full adder cells. Using H-Spice and 90nm CMOS technology exhibits a significant decrease in the cell delay which can result in a considerable reduction in the Power-Delay Product (PDP). The PDP of multi-output design at 1.8v power supply is around 0.15 fem to joule that is 5% lower than conventional dynamic full adder cell and at least 21% lower than other static full adders.

Provided by: International Research Publication House (IRPH) Topic: Hardware Date Added: Mar 2012 Format: PDF

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