Implementation of High Performance Spanning Tree Adder Using Quaternary Logic
The adder is the critical element in most digital circuit designs including digital signal processor and microprocessor data path unit. As such, extensive research and usage continuous, it is focused on improving the performance of the adder. Parallel prefix adders are known to have the best performance. This paper investigates parallel prefix adder i.e. spanning tree adders. In existing VLSI implementation, the spanning tree adder is implemented using normal full adders. For implementing existing 16 bit addition design it requires 16 normal full adders.