Implementation of High Speed Low Power Vedic Multiplier Using Reversible Logic

Provided by: International Journal of Advance Research in Science and Engineering (IJARSE)
Topic: Hardware
Format: PDF
Multiplication is an operation much needed in digital signal processing for various applications. Here the authors present a high speed Vedic multiplier which is efficient in terms of speed, making use of Urdhva Tiryagbhyam, a sutra for multiplication from Vedic math's. It is a simple architecture coupled with increased speed forms an unparalleled combination for serving any complex multiplication computation. Tagged with these highlights, power dissipation can be reduced by implementing this with reversible logic. Power dissipation is another important constraint in an embedded system which cannot be neglected.

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