Implementation of High Speed Pipelined ADC Architecture for I-UWB Receiver

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Provided by: Institute of Research and Journals (IRAJ)
Topic: Hardware
Format: PDF
In this paper, the authors propose a 4-bit pipelined ADC that provides the high speed conversion needed in UWB applications with sampling frequency of the order 60Gbps. The pipelined ADC designed uses a high speed 1-bit comparator, wide band operational amplifier, sampling circuit and a high speed buffer. The individual blocks are designed using 130nm CMOS low power library cells. The individual blocks are designed to operate at a frequency greater than 60Gbps sampling rate.
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