Implementation of High Throughput Radix-16 FFT Processor
The extension of radix-4 algorithm to radix-16 to achieve the high throughput of 2.59 giga-samples/s for WPAN's. The authors are also reformulating radix-16 algorithm to achieve low-complexity and low area cost and high performance. Radix-16 FFT is obtained by cascaded the radix-4 butterfly units. It facilitates low-complexity realization of radix-16 butterfly operation and high operation speed due to its optimized pipelined structure. Besides, a new three-stage multiplier for twiddle factor multiplication is also proposed, which has lower area and power consumption than conventional complex multipliers.