IT Society of India (ITSI)
The Itoh-Tsujii multiplicative inverse Algorithm (ITA) forms an integral component of several cryptographic implementations such as elliptic curve cryptography. For binary fields generated by irreducible trinomials, this paper modifies Itho-Tsuji Algorithm (ITA) for efficient implementation of FPGA. Efficiency is obtained by using FPGA resources better and shorter addition chains. The quad circuit is use for better utilization of FPGA resources as compared to squarer circuit without increase in area, but both circuits has same delay. The proposed paper is also shown to be scalable with respect to field sizes.