Provided by: International Journal of Innovative Research in Science, Engineering and Technology (IJIRSET)
Date Added: Feb 2014
For efficient hardware implementation many designers designs several multiplier structure based on different techniques. But these designs are achieving only 30% of power reduction and 28% of area reduction. In this paper, the authors propose a low complexity and low latency multiplier in order to reduce the requirement of power and area. The proposed paper is fully based on the Distributed Arithmetic Algorithm (DAA) which provides the better performance than the existing designs. The proposed design will be coded in verilogHDL and synthesized in Xilinx ISE9.2i. From the synthesized result they will prove the modified structure that requires less area and less power than the existing ones.