International Journal of Computer Applications
The insist for portable devices is fulfilled by the growing CMOS technology. As the size of the transistor shrinks, the leakage power component augments exponentially. Thus, it becomes a critical metric for the future technologies. This paper deals with the techniques like gated VDD, AVLS, AVLG and AVL for reducing leakage power. These techniques are implemented on 8-bit ALU. 80% of cutback in leakage power can be achieved by applying proposed technique with minimum delay and area overhead. The circuit is simulated on Cadence (R) Virtuoso (R) in 90 nanometer CMOS technology.