Implementation of Low Power All Digital Phase Locked Loop

Provided by: The International Journal of Innovative Research in Computer and Communication Engineering
Topic: Hardware
Format: PDF
Phase locked loop is a familiar circuit for high frequency application and very short interlocking time. In this paper, the authors have implemented and analyzed All Digital Phase Locked Loop (ADPLL), as the present applications requires a low cost, low power and high speed phase locked loops. The design is synthesized in Xilinx ISE software. The pure digital phase locked loop is attractive because it is less sensitive to noise and operating conditions than its analog counterpart.

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