Implementation of Low-Power and Area-Efficient 64bit Carry Select Adder

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Provided by: International Journal of Engineering Sciences & Research Technology (IJESRT)
Topic: Hardware
Format: PDF
Now-a-days, hottest area of research in VLSI (Very Large Scale Integration) system is design of the area, high-speed and power-efficient data path logic systems. All processor consisting of Arithmetic and Logical Unit (ALU) and adder plays an important role for design of ALU. In digital adders, the speed of addition is limited by the time required to send a carry through the adder. Carry SeLect Adder (CSLA) is an efficient is used for data-processing processors to perform fast arithmetic functions. The proposed work reduces area and power consumption to a great extent with the help of a simple Ripple Carry Adder (RCA) and gate-level architecture.
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