Implementation of Low Power and High Speed Encryption Using Crypto-Hardware

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Provided by: International Journal of Modern Engineering Research (IJMER)
Topic: Security
Format: PDF
Cryptographic algorithms such as International Data Encryption Algorithm (IDEA) have found various applications in secure transmission of the data in networked instrumentation and distributed measurement systems. Modulo 2n +1 multiplier and squarer play a pivotal role in the implementation of such crypto-algorithms. In this work, an efficient hardware design of the IDEA (International Data Encryption Algorithm) using novel modulo 2n + 1 multiplier and squarer as the basic modules is proposed for faster, smaller and low-power IDEA hardware circuits. Novel hardware implementation of the modulo 2n + 1 multiplier is shown by using the efficient compressors and sparse tree based inverted end around carry adders is given.
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