Implementation of Low Power, Low Delay Fused Add-Multiply Operator Using Prefix Adders
In many Digital Signal Processing (DSP) applications, complex arithmetic operations are used. To increase the performance and to reduce the complexity of arithmetic operations, the authors designed a Fused Add-Multiply (FAM) operator which directly recodes the sum of two numbers in its Modified Booth (MB) form and uses Wallace carry save adder for the partial product addition. The proposed paper focuses on FAM design by using prefix adders at the last stage of partial product addition which reduces both power consumption and delay leading to more efficient design for the purpose of low power applications.
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