Implementation of Modified Booth Recoded Wallace Tree Multiplier for fast Arithmetic Circuits

Provided by: International Journal of Advanced Research in Computer Science and Software Engineering (IJARCSSE)
Topic: Hardware
Format: PDF
Power consumption has become a critical concern in today's VLSI system design. The growing market for fast floating-point co-processors, digital signal processing chips, and graphics processor has created a demand for high speed and area-efficient multipliers. The modified booth recoding method is widely used to generate the partial products for implementation of large parallel multipliers, which adopts the parallel encoding scheme. A Wallace tree multiplier is an improved version of tree based multiplier architecture and uses carry save addition algorithm to reduce the latency.

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