International Journals of Advanced Information Science and Technology (IJAIST)
Addition is a fundamental arithmetic operation used in VLSI design systems like data process unit, microprocessor and DSP architecture. In VLSI design adders are the most critical components and attention should be focused in designing them. This paper deals with implementing carry look-ahead adder with 4-bits, 8-bits, 16-bits, 32-bits and 64-bits and 128-bits using Verilog platform. The designed carry look-ahead adders are simulated using multi-sim 5.7g and the sum generation and carry propagation are recorded. It is observer that the designed carry look-ahead adders performance is better when compared with traditional carry look-ahead adder.