Implementation of Novel Ultra-Low Power and High-Speed 1-Bit Full Adder Cell
In this paper, the authors present a novel ultra-low power and high speed 1-bit full-adder, which is designed only based on pass transistor logic. The main advantages of this design are very low propagation delay and ultra-low consumption power, which lead to achieve lower PDP and EDP than that of other. Intensive HSPICE simulation indicates that the new full-adder consumes around 70% less power than 14T adder; moreover its EDP 83% is lesser than 28T full-adder. They have compared some of the most popular full-adders like 28T, CPL, SS16T, 10T, and 14T to the proposed full-adder. Simulation has been carried out by HSPICE in 0.18Î¼m technology at 1.8V supply voltage.
Provided by: IDOSI Topic: Hardware Date Added: Mar 2015 Format: PDF