Implementation of Secure Hash Algorithm-1 Using FPGA
Hash functions play a significant role in today's cryptographic applications. SHA (Secure Hash Algorithm) is famous message compress standard used in computer cryptography, it can compress a long message to become a short message abstract. In this paper, SHA- 1 is implemented using Verilog HDL (Hardware Description Language). The SHA-1 Verilog source code is divided into three modules, namely Initial, Round and Top module. The Verilog code is synthesized on Virtex5 FPGA using Xilinx ISE 14.2 software tool.