Implementation of Trinary/Quaternary Addition Using Multivalue Logic Digital Circuit

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Provided by: International Journal of Computer Applications
Topic: Hardware
Format: PDF
Objective of multivalve logic design is to reduce number of gates needed and also to reduce interconnect path length. Interconnect path consist of the largest number of gates from input to output. The reason of these two objectives is that they will give extremely good properties when implemented in VLSI. Reducing number of gates will reduce the chip area, and minimizing interconnect path length will give opportunity to use highest clock frequency. In this paper, quaternary to binary and binary to quaternary converter are designed.
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