Implementation of USB 3.0 SuperSpeed Physical Layer using Verilog HDL

In this proposed design it mainly includes USB 3.0, physical layer along with USB 2.0 functionality with super speed functionality. Physical layer mainly contains PCI express and PIPE interface. This proposed design transferred data from transmitter to receiver serially. This design manages to transfer data either on 2.5GT/s or on 5.0GT/s depends upon the mode and rate. The design generates clock that runs on two different frequencies i.e. 125MHz and 250MHz that used to transfer data on parallel interface.

Provided by: International Journal of Computer Applications Topic: Hardware Date Added: Jun 2014 Format: PDF

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