Implementation on FPGA Area-Delay Efficient Architecture of CSLA

Provided by: International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (IJAREEIE)
Topic: Hardware
Format: PDF
In the design of VLSI, area and delay is play important role and the field of VLSI less delay and low area is required adder unit in data processing processor for performing fast arithmetic operation. Architecture of CSLA, there is chance to reduce area and delay which is based on sum generation unit and carry generation unit. In this paper, 128-bit, 64-bit, 32-bit and 16-bit conventional CSLA, modified CSLA and proposed CSLA architecture have been implemented on FPGA and compared result in term area that is of count of gate and delay. The proposed design has reduced area and delay.

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