Implementation on Low Power Design Using Comparator for VLSI Design Circuit

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Provided by: The International Journal of Innovative Research in Computer and Communication Engineering
Topic: Hardware
Format: PDF
An 8-bit 5GS/s streak simple to-ADvanced Converter (ADC) is composed and reproduced in a 0.18µm CMOS innovation. Low-swing operation both in the simple and the computerized hardware brings about fast low power operation. The ADC disperses 30mW force from a 3.2V supply while working at 5GHz. Balanced averaging is utilized to minimize the impact of comparator balances. The estimation of greatest differential and indispensable nonlinearities (DNL and INL) of the flash ADC are 0.2 LSB and 0.5 LSB separately.
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