Implementing a Functional/Timing Partitioned Microprocessor Simulator with an FPGA

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Provided by: Massachusetts Institute of Technology
Topic: Hardware
Format: PDF
When creating a microarchitectural simulator, one desires three things: confidence in correctness, speed of design, and speed of simulation. The first requirement is necessary for accurate experimentation. The second impacts the architect's ability to perform microarchitectural exploration by rapidly describing a range of systems. The third affects the number of simulations that can be profitably run for a particular systems, and thus the statistical confidence in their evaluation results. One approach is to divide the simulator into two partitions: a functional partition and a timing partition. The functional partition is essentially a pipelined abstract execution engine, which allows dataflow-valid executions through an idealized pipeline.
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