Implementing a Hybrid SRAM / EDRAM NUCA Architecture

Provided by: Universitat Rostock
Topic: Storage
Format: PDF
Advances in technology allowed for integrating DRAM-like structures into the chip, called embedded DRAM (eDRAM). This technology has already been successfully implemented in some GPUs and other graphic-intensive SoC, like game consoles. The most recent processor from IBM R, POWER7, is the first general-purpose processor that integrates an eDRAM module on the chip. In this paper, the authors propose a hybrid cache architecture that exploits the main features of both memory technologies, speed of SRAM and high density of eDRAM. They demonstrate, that due to the high locality found in emerging applications, a high percentage of data that enters to the on-chip last-level cache are not accessed again before they are evicted.

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