Implementing Efficient Embedded Logic in Low Power Twin Dynamic Pulsed Hybrid Flip-Flop
Flip flops are critical timing elements in digital circuits which have large impact on circuit speed and power consumption. The parameters to be considered while designing a flip flop is power and delay. The proposed Twin Dynamic pulsed hybrid Flip Flop (TDFF) eliminates the large capacitance present in the precharge node due to its split dynamic node structure. It eliminates the redundant power dissipation present in Cross Charge control Flip Flop (XCFF). TDFF provides short latency and logic functions can be incorporated with minimum delay.