Vienna University of Technology
The fault and failure models as well as their semantics within the VLSI community and the distributed systems/algorithms community are quite different. Pointing out the mismatch of those fault respectively failure models is the main part of this work. The impact of the failure model in terms of hardware implementation effort and system complexity will be shown for different VLSI implementations of distributed algorithms. However, still, there are a lot of open questions left, mostly related to the coverage analysis of hardware implemented fault-tolerant algorithms.