Improved Carry Select Adder With Reduced Area and Low Power Consumption
Power dissipation is one of the most important design objectives in integrated circuits, after speed. As adders are the most widely used components in such circuits, design of efficient adder is of much concern for researchers. This paper presents performance analysis of different fast adders. The comparison is done on the basis of three performance parameters i.e. area, speed and power consumption. The authors present a modified carry select adder designed in different stages. Results obtained from modified carry select adders are better in area and power consumption.