University of California, Los Angeles (Anderson)
Improving arithmetic circuits on FPGAs is one of the main imperatives of FPGA vendors. Augmenting logic cells with dedicated arithmetic components such as adders and carry chains indicates the need for such improvements. In this paper, the authors showed how the carry chains in the state-of-the-art Altera FPGAs could be exploited for synthesis of compressor trees. In this paper, they proposed Generalized Parallel Counters (GPCs) as the building blocks and mapped them to logic cells of FPGA using LUTs and carry chains. In this paper, they propose a novel technique to increase the logic density of compressor tree synthesis by sharing the logic cells between two neighbor GPCs in a chain.