Improving Cache Locality for Thread-Level Speculation

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Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
With the advent of Chip Multi-Processors (CMPs), Thread-Level Speculation (TLS) remains a promising technique for exploiting this highly multithreaded hardware to improve the performance of an individual program. However, with such speculatively-parallel execution the cache locality once enjoyed by the original uniprocessor execution is significantly disrupted: for TLS execution on a four-processor CMP, the authors find that the data-cache miss rates are nearly four-times those of the uniprocessor case, even though TLS execution utilizes four private data caches (i.e., four-fold greater cache capacity).
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