Improving DRAM Performance by Parallelizing Refreshes with Accesses

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Provided by: Carnegie Mellon University
Topic: Storage
Format: PDF
Modern main memory is predominantly built using Dynamic Random Access Memory (DRAM) cells. A DRAM cell consists of a capacitor to store one bit of data as electrical charge. The capacitor leaks charge over time, causing stored data to change. As a result, DRAM requires an operation called refresh that periodically restores electrical charge in DRAM cells to maintain data integrity. Modern DRAM cells are periodically refreshed to prevent data loss due to leakage. Commodity DDR (Double Data Rate) DRAM refreshes cells at the rank level. This degrades performance significantly because it prevents an entire DRAM rank from serving memory requests while being refreshed.
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