Improving Energy Efficiency of Write-asymmetric Memories by Log Style Write
The significant scaling challenges of conventional memories, i.e., SRAM and DRAM, motivated the research on emerging memory technologies. Many promising memory technology candidates, however, suffer from a common issue in their write operations: the switching processes at different write operations are asymmetric. Using a pessimistic design corner to cover the worst case of a write operation incurs large power and performance cost in the existing emerging memory technology designs. In this paper, the authors propose a universal log style write methodology to mitigate this asymmetry issue by operating two switching processes in separate stages.