Improving FPGA Performance for Carry-Save Arithmetic

Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP applications, and further opportunities to exploit it can be exposed through systematic data flow transformations that can be applied by a hardware compiler. Field-Programmable Gate Arrays (FPGAs), however, are not particularly well suited to carry-save arithmetic. To address this concern, the authors introduce the \"Field Programmable Counter Array\" (FPCA), an accelerator for carry-save arithmetic intended for integration into an FPGA as an alternative to DSP blocks.

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