Improving Min-Sum LDPC Decoding Throughput by Exploiting Intra-Cell Bit Error Characteristic in MLC NAND Flash Memory

Provided by: Institute of Electrical & Electronic Engineers
Topic: Storage
Format: PDF
Multi-Level per Cell (MLC) technique significantly improves storage density, but also poses new challenge to data integrity in NAND flash memory. Therefore, Low-Density Parity-Check (LDPC) code and soft-decision memory sensing have become indispensable in future NAND flash-based solid state drive design. However, these more powerful technologies inevitably increase the memory read latency and hence degrade the decoding throughput. Motivated by intra-cell unbalanced bit error probability and data dependency in MLC NAND flash memory, this paper proposes two techniques, i.e. intra-cell data placement interleaving and intra-cell data dependency aware min-sum decoding, to effectively improve the throughput of LDPC decoding.

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