Improving Reliability of Non-Volatile Memory Technologies Through Circuit Level Techniques and Error Control Coding
Non-volatile resistive memories, such as Phase-change RAM (PRAM) and spin transfer torque RAM (STT-RAM), have emerged as promising candidates because of their fast read access, high storage density, and very low standby power. Unfortunately, in scaled technologies, high storage density comes at a price of lower reliability. In this paper, the authors first study in detail the causes of errors for PRAM and STT-RAM. They see that while for Multi-Level Cell (MLC) PRAM, the errors are due to resistance drift, in STT-RAM they are due to process variations and variations in the device geometry. They develop error models to capture these effects and propose techniques based on tuning of circuit level parameters to mitigate some of these errors.