Improving STT MRAM Storage Density Through Smaller-Than-Worst-Case Transistor Sizing

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Provided by: Association for Computing Machinery
Topic: Storage
Format: PDF
In this paper, the authors present a technique to improve the storage density of Spin-Torque Transfer (STT) Magnetoresistive Random Access Memory (MRAM) in the presence of significant Magnetic Tunneling Junction (MTJ) write current threshold variability. In conventional design practice, the nMOS transistor within each memory cell is sized to be large enough to carry a current larger than the worst-case MTJ write current threshold, leading to an increasing storage density penalty as the technology scales down. To mitigate such variability induced storage density penalty, this paper presents a smaller-than worst-case transistor sizing approach with the underlying theme of jointly considering memory cell transistor sizing and defect tolerance.
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