Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures

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Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
With the shift towards Deep Sub-Micron (DSM) technologies, the increase in leakage power and the adoption of power-aware design methodologies have resulted in potentially significant variations in power consumption under different Process, Voltage and Temperature (PVT) corners. In this paper, the authors first investigate the impact of PVT corners on power consumption at the System-on-Chip (SoC) level, especially for the on-chip communication infrastructure. Given a target technology library, they then show how it is possible to \"Scale up\" and abstract the PVT variability at the system level, allowing characterization of the PVT-aware design space early in the design flow.
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