Increasing Speed with Low-Power Multiplier

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Provided by: International Journal of Research and Applications (IJRA)
Topic: Hardware
Format: PDF
In this paper, the authors present the design exploration of a Spurious-Power Suppression Technique (SPST) which can dramatically reduce the power dissipation of combinational VLSI designs for multimedia/DSP purposes. The proposed SPST separates the target designs into two parts, i.e., the Most Significant Part and Least Significant Part (MSP and LSP), and turns off the MSP when it does not affect the computation results to save power. There are different entities that one would like to optimize when designing a VLSI circuit.
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