Increasing the Performance of Integrated Circuits by Using Error Lenient Adder
The probability of errors in the present VLSI technology is very high and it is increasing with technology scaling. Removing all errors is very expensive task and is not required for certain applications. There are certain application where the approximate result is acceptable e.g. image processing and video processing. For these applications Error Tolerant Adder (ETA) is proposed which provide approximate result at very high speed than the convention adder. The proposed adder provides improvement in delay, power and area at the same time at the cost of accuracy. Simulation result shows improvement in delay, power and area respectively over convention adder.