Provided by: Universite Bordeaux 1
In this paper, the authors complement this work by analyzing an implementation of the AES s-box, in the DDSLL dual-rail logic style, using the same 65-nanometer technology. For this purpose, they first compare the performance results of the static CMOS and dual-rail s-boxes. They show that full custom design allows to nicely mitigate the performance drawbacks that are usually reported for dual-rail circuits. Next, they evaluate the side-channel leakages of these s-boxes, using both simulations and actual measurements. They take advantage of state-of-the-art evaluation tools, and discuss the quantity and nature (e.g. linearity) of the physical information they provide.