Georgia Institute of Technology
Processor power is a complex function of device, packaging, micro-architecture, and application. Typical approaches to power simulation require detailed micro-architecture models to collect the statistical switching activity counts of processor components. In many-core simulations, the detailed core models are the main simulation speed bottleneck. In this paper, the authors propose an instruction-based energy estimation model for fast and scalable energy simulation. Importantly, in this approach the dynamic energy is modeled as a combination of three contributing factors: physical, micro-architectural, and workload properties.