Instruction Set Extension Exploration in Multiple-Issue Architecture

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Provided by: edaa
Topic: Hardware
Format: PDF
Recently, next-generation digital entertainment and mobile communication devices are driving the need for high-performance processing solutions. To satisfy high-performance computing demand in modern embedded devices, current embedded processor architectures provide designer with possibility either to define customized Instruction Set Extension (ISE) or to increase instruction issue width. Previous papers have shown that deploying ISE in multiple-issue architecture can significantly improve performance. However, identifying ISE for multiple-issue architecture by using current ISE exploration algorithms will result in unnecessary waste of silicon area and limitation of performance improvement.
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