Instruction Set Simulator for MPSoCs Based on NoCs and MIPS Processors

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Provided by: Darmstadt University of Technology
Topic: Hardware
Format: PDF
Even though Multi-Processor System-on-Chip (MPSoC) is a hot topic for a decade, Instruction Set Simulators (ISSs) for it are still scarce. Data exchange among processors and synchronization directives are some of the most required characteristics that ISSs for MPSoCs should supply to really make use of the processing power provided by the parallel execution of processors. In this paper, a framework for instantiating ISSs compatible with the MIPS processor is presented. Communication among different ISS instances is implemented by message passing, which is actually performed by packets being exchanged over a NoC.
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