Integrated Floorplanning, Module-Selection and Architecture Generation for Reconfigurable Devices

In this paper, the authors concern with the application of formal optimisation methods to the design of mixed-granularity FPGAs. In particular, they investigate the appropriate mix and floorplan of heterogeneous elements: multipliers, RAMs, and LUT-based logic, in order to maximize the performance of a set of DSP benchmark applications, given a fixed silicon budget. A mathematical programming framework is introduced, along with a set of heuristics, capable of providing upper-bounds on the achievable reconfigurable-to-fixed-logic performance ratio.