Inter-Core Cooperative TLB Prefetchers for Chip Multiprocessors

Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
To avoid high-latency accesses to Operating System (OS) page tables storing virtual-to-physical page translations, processor Memory Management Units (MMUs) store commonly used translations in instruction and data Translation Lookaside Buffers (TLBs). While past work has addressed various options for TLB placement and lookup, most contemporary systems place them in parallel with the first-level cache. Due to their long miss penalties, TLB behavior affects processor performance significantly. Translation Lookaside Buffers (TLBs) are commonly employed in modern processor designs and have considerable impact on overall system performance.

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